1. Field of the Invention
The present invention relates to a clock control circuit and an integrated circuit, and more particularly to a clock control circuit for controlling a clock signal to be supplied to a target circuit to reduce a consumption power and to an integrated circuit.
2. Description of the Related Art
A clock signal is distributed to flip-flop circuits and the like in an integrated circuit. A flip-flop circuit receives a clock signal in order to hold input data synchronously with the clock signal, and even if the data to be held in the flip-flop circuit does not change, the clock signal changes so that an unnecessary power is consumed. It is therefore desired from the viewpoint of power consumption that a clock signal should be supplied to the target circuit in an integrated circuit only during the necessary and minimum period.
A clock enabler, which is a combination of, e.g., a latch circuit and a logical gate, has been proposed in order to regulate the supply of a clock signal. In this clock enabler, an inverted signal of a clock signal is input to a gate terminal of the latch circuit and an enable signal is input to a data input terminal of the latch circuit, to obtain a corrected enable signal from a data output terminal of the latch circuit. The logical gate generates a logical sum of the corrected enable signal and clock signal to obtain a clock signal with a regulated period. A change in the state of the corrected enable signal occurs only while the clock is in a low level state, so that the waveform (duty ratio) of the clock signal generated by the logical gate is the same as that of the original clock signal. The clock signal with the regulated period can therefore be obtained without being influenced by a timing shift of the original enable signal (for example, refer to FIG. 1 of Japanese Patent Application Publication No. H09-284101).